MAX1084AESA+【PDF 15/16 页】IC ADC 10BIT 400KSPS 8-SOIC

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MAX1084/MAX1085

400ksps/300ksps, Single-Supply, Low-Power,

Serial 10-Bit ADCs with Internal Reference

_______________________________________________________________________________________

_______________Detailed Description

Converter Operation

The MAX1084/MAX1085 use an input track/hold (T/H)

and successive-approximation register (SAR) circuitry to

convert an analog input signal to a digital 10-bit output.

Figure 3 shows the MAX1084/MAX1085 in their simplest

configuration. The internal reference is trimmed to 2.5V.

The serial interface requires only three digital lines

(SCLK, CS, and DOUT) and provides an easy interface to

microprocessors (Ps).

The MAX1084/MAX1085 have two modes: normal and

shutdown. Pulling SHDN low shuts the device down and

reduces supply current to 2A (typ); pulling SHDN high

puts the device into operational mode. Pulling CS low ini-

tiates a conversion that is driven by SCLK. The conver-

sion result is available at DOUT in unipolar serial format.

The serial data stream consists of three zeros, followed

by the data bits (MSB first). All transitions on DOUT

occur 20ns after the rising edge of SCLK. Figures 8 and

9 show the interface timing information.

Analog Input

Figure 4 shows the sampling architecture of the ADC’s

comparator. The full-scale input voltage is set by the

internal reference (VREF = +2.5V).

Track/Hold

In track mode, the analog signal is acquired and stored

in the internal hold capacitor. In hold mode, the T/H

switch opens and maintains a constant input to the

ADC’s SAR section.

During acquisition, the analog input AIN charges

capacitor CHOLD. Bringing CS low ends the acquisition

interval. At this instant, the T/H switches the input side

of CHOLD to GND. The retained charge on CHOLD repre-

sents a sample of the input, unbalancing node ZERO at

the comparator’s input.

In hold mode, the capacitive digital-to-analog converter

(DAC) adjusts during the remainder of the conversion

cycle to restore node ZERO to 0 within the limits of 10-

bit resolution. This action is equivalent to transferring a

charge from CHOLD to the binary-weighted capacitive

DOUT

DGND

CLOAD = 20pF

DGND

VDD

b) HIGH-Z TO VOL AND VOH TO VOL

a) HIGH-Z TO VOH AND VOL TO VOH

DOUT

DGND

CLOAD = 20pF

DGND

VDD

b) VOLTO HIGH-Z

a) VOH TO HIGH-Z

Figure 1. Load Circuits for DOUT Enable Time

Figure 2. Load Circuits for DOUT Disable Time

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